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A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.

, , , , , , , , , , , , , , , , and . J. Solid-State Circuits, 55 (1): 157-166 (2020)

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Self-motion utilization for reducing vibration of a structurally flexible redundant robot manipulator system., and . Robotica, 16 (6): 669-677 (1998)Residual vibration reduction for a flexible structure using a modified input shaping technique., and . Robotica, 20 (5): 553-561 (2002)Sound direction estimation using an artificial ear for robots., , and . Robotics and Autonomous Systems, 59 (3-4): 208-217 (2011)Experimental evaluation of time-varying impulse shaping with a two-link flexible manipulator., and . Robotica, 14 (3): 339-345 (1996)Fourier-based optimal design of a flexible manipulator path to reduce residual vibration of the endpoint., and . Robotica, 11 (3): 263-272 (1993)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM., , , , , , and . DAC, page 91:1-91:6. ACM, (2015)A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking., , , , , , , , , and 29 other author(s). J. Solid-State Circuits, 54 (1): 197-209 (2019)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 55 (1): 157-166 (2020)PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion., , , , , , and . ISCAS, page 1902-1905. IEEE, (2008)Residual Vibration Reduction of Time-Varying Flexible Structures by Input Shaping., and . JRM, 6 (3): 220-229 (1994)