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Disambiguation of "Lim, Ji-Hoon"

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A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 434-435. IEEE, (2010)

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Jaekeun Lim University of Stuttgart

Yanjun Ji University of Stuttgart

Carlos Eduardo Jimenez University of Stuttgart

Chuhan Jiao University of Stuttgart

Chenming Jiang University of Stuttgart

 

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Design of Cyber Attack Precursor Symptom Detection Algorithm through System Base Behavior Analysis and Memory Monitoring., , , , and . FGIT-FGCN (2), volume 120 of Communications in Computer and Information Science, page 276-283. Springer, (2010)A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface., , , , , , , , , and . J. Solid-State Circuits, 51 (8): 1890-1901 (2016)An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , and 14 other author(s). J. Solid-State Circuits, 43 (1): 121-131 (2008)A Study on Markerless AR-Based Infant Education System Using CBIR., and . SUComS, volume 78 of Communications in Computer and Information Science, page 52-58. Springer, (2010)A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , and 20 other author(s). J. Solid-State Circuits, 46 (1): 107-118 (2011)A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique., , , , and . IEICE Transactions, 96-C (2): 277-284 (2013)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction., , , , , , , , , and 20 other author(s). ISSCC, page 434-435. IEEE, (2010)A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs., , , , , , , , and . IEEE Trans. on Circuits and Systems, 63-II (2): 141-145 (2016)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , and 19 other author(s). ISSCC, page 492-617. IEEE, (2007)A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips., , , , and . IEICE Transactions, 90-C (3): 644-648 (2007)