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pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.

S. Bae, K. Park, J. Ihm, H. Song, W. Lee, H. Kim, K. Kim, Y. Park, M. Park, H. Lee, S. Bang, G. Moon, S. Hwang, Y. Cho, S. Hwang, D. Kim, J. Lim, J. Kim, S. Kim, S. Jang, J. Choi, Y. Jun, K. Kim, and S. Cho. J. Solid-State Circuits, 43 (1): 121-131 (2008)

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Sumee Park

Philipp Ilzhöfer University of Stuttgart

Soo Yong Park University of Stuttgart

Tobias Ilg University of Stuttgart

Elisa Ilg University of Stuttgart

Other publications of authors with the same name

A Wormhole Router with Embedded Broadcasting Virtual Bus for Mesh Computers.B. Kim, J. Choi, K. Park, and K. Park. Parallel Processing Letters, 10 (1): 29-37 (2000)HMM and Rule-Based Hybrid Intruder Detection Approach by Synthesizing Decisions of Sensors.K. Kim, K. Park, Y. Jeong, J. Hong, H. Kim, and W. Kim. IJDSN, (2013)A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces.B. Kim, L. Kim, K. Park, Y. Jun, and S. Cho. J. Solid-State Circuits, 44 (5): 1522-1530 (2009)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.J. Heo, K. Kim, D. Lee, C. Lee, D. Moon, K. Kim, J. Baek, S. Yoon, H. Yang, K. Kim and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.T. Oh, H. Chung, J. Park, K. Lee, S. Oh, S. Doo, H. Kim, C. Lee, H. Kim, J. Lee and 10 other author(s). J. Solid-State Circuits, 50 (1): 178-190 (2015)A DLL with Jitter-Reduction Techniques for DRAM Interfaces.B. Kim, L. Kim, K. Park, Y. Jun, and S. Cho. ISSCC, page 496-497. IEEE, (2007)A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme.K. Oh, L. Kim, K. Park, Y. Jun, J. Choi, and K. Kim. J. Solid-State Circuits, 44 (8): 2222-2232 (2009)A Methodology Combining Cosine Similarity with Classifier for Text Classification.K. Park, J. Hong, and W. Kim. Applied Artificial Intelligence, 34 (5): 396-411 (2020)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.Y. Peng, B. Ku, Y. Park, K. Park, S. Jang, J. Choi, and S. Lim. DAC, page 91:1-91:6. ACM, (2015)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.S. Bae, Y. Sohn, T. Oh, S. Kim, Y. Yang, D. Kim, S. Kwak, H. Seol, C. Shin, M. Park and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)

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Disambiguation of "Park, Kwang-Il"

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An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.

Please choose a person to relate this publication to

Sumee Park

Philipp Ilzhöfer University of Stuttgart

Soo Yong Park University of Stuttgart

Tobias Ilg University of Stuttgart

Elisa Ilg University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Park, Kwang-Il"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.

Please choose a person to relate this publication to

Sumee Park

Philipp Ilzhöfer University of Stuttgart

Soo Yong Park University of Stuttgart

Tobias Ilg University of Stuttgart

Elisa Ilg University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion.