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Disambiguation of "Sohn, Young-Soo"

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A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.

, , , , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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Mike Söhner University of Stuttgart

Dr. Felicitas Söhner University of Stuttgart

Ekta Sood University of Stuttgart

Soo Yong Park University of Stuttgart

Moon Young Jeong University of Stuttgart

 

Other publications of authors with the same name

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)Field emission characteristics of an oxidized porous polysilicon field emitter using the electrochemical oxidation process., , , , , and . Microelectronics Journal, 37 (9): 993-996 (2006)A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , and 20 other author(s). J. Solid-State Circuits, 46 (1): 107-118 (2011)A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW., , , , , , , , , and 19 other author(s). ISSCC, page 498-500. IEEE, (2011)A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s., , , , , , , , and . IEEE Trans. on Circuits and Systems, 63-I (1): 122-133 (2016)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 52 (1): 250-260 (2017)Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 53 (10): 2906-2916 (2018)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface., , , , , , and . J. Solid-State Circuits, 46 (9): 2053-2063 (2011)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution., , , , , , , , , and 11 other author(s). ISSCC, page 316-317. IEEE, (2016)