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A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications., , and . IEEE Trans. on Circuits and Systems, 61-II (1): 6-10 (2014)A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction., , , and . CICC, page 1-4. IEEE, (2010)Performance Test of LTE-R Railway Wireless Communication at High-Speed (350 km/h) Environments., , , , and . ICUFN, page 637-640. IEEE, (2018)Design of a 1-Volt and µ-power SARADC for Sensor Network Application., , and . ISCAS, page 3852-3855. IEEE, (2007)A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction., , , and . J. Solid-State Circuits, 46 (8): 1881-1892 (2011)Real-time 3D human pose recognition from reconstructed volume via voxel classifiers., , , , , , , and . Three-Dimensional Image Processing, Measurement (3DIPM), and Applications, volume 9013 of SPIE Proceedings, page 901306. SPIE, (2014)A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process., , , , , , , , , and 16 other author(s). VLSI Circuits, page 147-148. IEEE, (2018)Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC., and . IET Circuits, Devices & Systems, 13 (8): 1277-1283 (2019)A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 55 (1): 157-166 (2020)A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface., , , , , , , , , and 6 other author(s). VLSIC, page 182-. IEEE, (2015)