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Disambiguation of "Park, Hong-June"

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A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.

, , , , , , , , and . IEEE Trans. on Circuits and Systems, 63-I (1): 122-133 (2016)

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Sumee Park

Hong Chen University of Stuttgart

Dr. -Ing. Richard Junesch University of Stuttgart

Soo Yong Park University of Stuttgart

Aisha Zahid Junejo University of Stuttgart

 

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A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier., , , , and . IEEE Trans. on Circuits and Systems, 60-II (3): 142-146 (2013)A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL., , , , , , , , , and . IEEE Trans. on Circuits and Systems, 58-II (10): 687-691 (2011)An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects., , , and . IEEE Trans. on Circuits and Systems, 62-I (5): 1335-1344 (2015)A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface., , , and . IEEE Trans. on Circuits and Systems, 60-II (2): 91-95 (2013)5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump., , , and . IEEE Trans. on Circuits and Systems, 58-II (5): 269-273 (2011)An Approximate Closed-Form Channel Model for Diverse Interconnect Applications., , , and . IEEE Trans. on Circuits and Systems, 61-I (10): 3034-3043 (2014)A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration., , , , , and . ISSCC, page 112-113. IEEE, (2008)An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface., , , , , , , and . ISSCC, page 136-138. IEEE, (2012)A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC., , , and . J. Solid-State Circuits, 47 (4): 875-883 (2012)A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines., , , , and . J. Solid-State Circuits, 47 (9): 2068-2079 (2012)