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A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.

, , , , , , , , and . IEEE Trans. on Circuits and Systems, 63-I (1): 122-133 (2016)

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A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s., , , , , , , , and . IEEE Trans. on Circuits and Systems, 63-I (1): 122-133 (2016)A New Colum Redundancy Scheme For Fast Access Time of 64-Mb DRAM., , , , , , , , and . ISCAS, page 1937-1940. IEEE, (1993)Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs., , , , , , , , , and 1 other author(s). VLSIC, page 1-2. IEEE, (2014)An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs., , , , , , , , , and 2 other author(s). IEICE Transactions, 94-C (10): 1690-1697 (2011)A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution., , , , , , , , , and 9 other author(s). J. Solid-State Circuits, 52 (1): 250-260 (2017)An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , and 14 other author(s). J. Solid-State Circuits, 43 (1): 121-131 (2008)Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 53 (10): 2906-2916 (2018)A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power., , , , , , , , , and 20 other author(s). ISSCC, page 378-380. IEEE, (2019)A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme., , , , , , , , , and 18 other author(s). ISSCC, page 38-40. IEEE, (2012)5.7 A 29nW bandgap reference circuit., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)