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A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.

I. Yi, S. Bae, M. Chae, S. Lee, Y. Jang, Y. Cho, Y. Sohn, J. Choi, S. Jang, B. Kim, J. Sim, and H. Park. VLSI Circuits, page 1-2. IEEE, (2016)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yi Wang University of Stuttgart

Philipp Ilzhöfer University of Stuttgart

Seda Yilmaz University of Stuttgart

Michael Minas University of Stuttgart

Kai Mindermann University of Stuttgart

Other publications of authors with the same name

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s.I. Yi, S. Lee, S. Bae, Y. Sohn, J. Choi, S. Jang, B. Kim, J. Sim, and H. Park. IEEE Trans. on Circuits and Systems, 63-I (1): 122-133 (2016)A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer.I. Yi, N. Miura, H. Fukuyama, and H. Nosaka. IEICE Transactions, 101-A (11): 1949-1951 (2018)A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface.S. Lee, J. Lim, I. Yi, Y. Jang, H. Jung, K. Kim, D. Kwon, B. Kim, J. Sim, and H. Park. J. Solid-State Circuits, 51 (8): 1890-1901 (2016)A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines.H. Jung, I. Yi, S. Lee, J. Sim, and H. Park. J. Solid-State Circuits, 47 (9): 2068-2079 (2012)A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination.I. Yi, S. Lee, S. Bae, Y. Sohn, J. Choi, B. Kim, J. Sim, and H. Park. IEEE Trans. on Circuits and Systems, 61-II (12): 987-991 (2014)A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation.I. Yi, N. Miura, H. Fukuyama, and H. Nosaka. A-SSCC, page 239-242. IEEE, (2018)An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.S. Lee, I. Yi, H. Jung, H. Lee, Y. Kim, Y. Kim, B. Kim, J. Sim, and H. Park. J. Solid-State Circuits, 49 (11): 2618-2630 (2014)A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.I. Yi, S. Bae, M. Chae, S. Lee, Y. Jang, Y. Cho, Y. Sohn, J. Choi, S. Jang, B. Kim and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)

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Disambiguation of "Yi, Il-Min"

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A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.

Please choose a person to relate this publication to

Yi Wang University of Stuttgart

Philipp Ilzhöfer University of Stuttgart

Seda Yilmaz University of Stuttgart

Michael Minas University of Stuttgart

Kai Mindermann University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Yi, Il-Min"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.

Please choose a person to relate this publication to

Yi Wang University of Stuttgart

Philipp Ilzhöfer University of Stuttgart

Seda Yilmaz University of Stuttgart

Michael Minas University of Stuttgart

Kai Mindermann University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.