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GPU-Accelerated Simulation of Small Delay Faults

, , , , and . IEEE transactions on computer-aided design of integrated circuits and systems, 36 (5): 829-841 (2017)
DOI: 10.1109/TCAD.2016.2598560

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Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. VLSI Syst., 24 (1): 38-49 (2016)A Testable Design of Logic Circuits under Highly Observable Condition., and . IEEE Trans. Computers, 41 (5): 654-659 (1992)A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits., , , , and . IEICE Transactions, 91-D (3): 667-674 (2008)Testing of k-FR Circuits under Highly Observable Condition., , and . IEICE Transactions, 78-D (7): 830-838 (1995)Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing., , , , , , and . J. Electronic Testing, 24 (4): 379-391 (2008)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (3): 455-463 (2011)CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing., , , , , , , and . Asian Test Symposium, page 99-104. IEEE Computer Society, (2009)Fault Diagnosis for Physical Defects of Unknown Behaviors., , , and . Asian Test Symposium, page 236-241. IEEE Computer Society, (2003)Session Summary III: Power-Aware Testing: Present and Future., and . Asian Test Symposium, page 220. IEEE Computer Society, (2012)