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Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

S. Wu, L. Wang, X. Wen, Z. Jiang, L. Tan, Y. Zhang, Y. Hu, W. Jone, M. Hsiao, J. Li, J. Huang, and L. Yu. IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (3): 455-463 (2011)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dr. rer. nat. Lei Wang University of Stuttgart

Zhe Wang University of Stuttgart

Dr. Dongren Wang University of Stuttgart

Xiwei Wang University of Stuttgart

FangFang Wang University of Stuttgart

Other publications of authors with the same name

Testing of Synchronizers in Asynchronous FIFO.H. Kim, L. Wang, Y. Wu, and W. Jone. J. Electronic Testing, 29 (1): 49-72 (2013)Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.X. Wen, K. Miyase, T. Suzuki, S. Kajihara, L. Wang, K. Saluja, and K. Kinoshita. J. Electronic Testing, 24 (4): 379-391 (2008)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.S. Wu, L. Wang, X. Wen, Z. Jiang, L. Tan, Y. Zhang, Y. Hu, W. Jone, M. Hsiao, J. Li and 2 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (3): 455-463 (2011)Logic BIST Architecture for System-Level Test and Diagnosis.J. Qian, X. Wang, Q. Yang, F. Zhuang, J. Jia, X. Li, Y. Zuo, J. Mekkoth, J. Liu, H. Chao and 5 other author(s). Asian Test Symposium, page 21-26. IEEE Computer Society, (2009)Test compression and logic BIST at your fingertips.S. Wu, L. Wang, J. Cho, Z. Jiang, and B. Sheu. ITC, page 2. IEEE Computer Society, (2005)A circular pipeline processing based deterministic parallel test pattern generator.K. Yeh, J. Huang, H. Chao, and L. Wang. ITC, page 1-8. IEEE Computer Society, (2013)Circuits for pseudoexhaustive test pattern generation.L. Wang, and E. McCluskey. IEEE Trans. on CAD of Integrated Circuits and Systems, 7 (10): 1068-1080 (1988)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.L. Wang, X. Wen, S. Wu, Z. Wang, Z. Jiang, B. Sheu, and X. Gu. IEEE Design & Test of Computers, 25 (2): 122-130 (2008)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.A. Tomita, X. Wen, Y. Sato, S. Kajihara, P. Girard, M. Tehranipoor, and L. Wang. Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator.K. Yeh, J. Huang, and L. Wang. J. Electronic Testing, 32 (5): 625-638 (2016)

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Disambiguation of "Wang, Laung-Terng"

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Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

Please choose a person to relate this publication to

Dr. rer. nat. Lei Wang University of Stuttgart

Zhe Wang University of Stuttgart

Dr. Dongren Wang University of Stuttgart

Xiwei Wang University of Stuttgart

FangFang Wang University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Wang, Laung-Terng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

Please choose a person to relate this publication to

Dr. rer. nat. Lei Wang University of Stuttgart

Zhe Wang University of Stuttgart

Dr. Dongren Wang University of Stuttgart

Xiwei Wang University of Stuttgart

FangFang Wang University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.