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Disambiguation of "Li, James Chien-Mo"

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Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

, , , , , , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (3): 455-463 (2011)

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Univ. -Prof. Dr. James Foster University of Stuttgart

M.Sc. Yunxuan Li University of Stuttgart

Yu Li University of Stuttgart

Zheng Li University of Stuttgart

Jie Li University of Stuttgart

 

Other publications of authors with the same name

Test Generation of Path Delay Faults Induced by Defects in Power TSV., , , , , and . Asian Test Symposium, page 43-48. IEEE Computer Society, (2013)CSER: BISER-based concurrent soft-error resilience., , , , , and . VTS, page 153-158. IEEE Computer Society, (2010)Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing., and . J. Low Power Electronics, 3 (2): 206-216 (2007)Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains.. IEEE Trans. Computers, 54 (11): 1467-1472 (2005)On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs., , , , , , , , , and . DFT, page 143-151. IEEE Computer Society, (2008)A new method for parameter estimation of high-order polynomial-phase signals., , , , and . Signal Processing, (2018)Survey of Scan Chain Diagnosis., , , and . IEEE Design & Test of Computers, 25 (3): 240-248 (2008)Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits., , , , and . ATS, page 181-186. IEEE Computer Society, (2015)Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 17 (4): 48:1-48:16 (2012)An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example., , , and . IEEE Trans. on Circuits and Systems, 59-I (8): 1644-1655 (2012)