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Disambiguation of "Wu, Shianling"

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Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

, , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 17 (4): 48:1-48:16 (2012)

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Hanchuan Wu University of Stuttgart

Yongxiang Wu University of Stuttgart

Tim Würtele University of Stuttgart

Amelie Wührl University of Stuttgart

PD Dr. phil. Joachim Wündisch University of Stuttgart

 

Other publications of authors with the same name

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). DFT, page 358-366. IEEE Computer Society, (2010)At-Speed Logic BIST Architecture for Multi-Clock Designs., , , , and . ICCD, page 475-478. IEEE Computer Society, (2005)A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing., , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)A Sequential Circuit Test Generation System., and . ITC, page 57-61. IEEE Computer Society, (1985)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Design & Test of Computers, 26 (1): 26-35 (2009)At-Speed Logic BIST for IP Cores., , , , , , , , and . DATE, page 860-861. IEEE Computer Society, (2005)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (3): 455-463 (2011)Logic BIST Architecture for System-Level Test and Diagnosis., , , , , , , , , and 5 other author(s). Asian Test Symposium, page 21-26. IEEE Computer Society, (2009)Lessons Learned from Practical Applications of BIST/B-S Technology., , , and . Asian Test Symposium, page 251-257. IEEE Computer Society, (1996)Test compression and logic BIST at your fingertips., , , , and . ITC, page 2. IEEE Computer Society, (2005)