Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Sheu, Boryau
add a person with the name Sheu, Boryau
 

Other publications of authors with the same name

Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Design & Test of Computers, 26 (1): 26-35 (2009)A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing., , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs., , , , , , , , , and . DFT, page 143-151. IEEE Computer Society, (2008)Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs., , , , , , , and . DFT, page 331-339. IEEE Computer Society, (2010)Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (2): 299-312 (2010)UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction., , , , , , and . ITC, page 8. IEEE Computer Society, (2005)Practical Challenges in Logic BIST Implementation., , , , , , , and . ATS, page 265. IEEE Computer Society, (2008)Test compression and logic BIST at your fingertips., , , , and . ITC, page 2. IEEE Computer Society, (2005)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Design & Test of Computers, 25 (2): 122-130 (2008)Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard., , , , , , , , , and 6 other author(s). ITC, page 1-9. IEEE Computer Society, (2008)