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Disambiguation of "Wen, Xiaoqing"

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Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.

, , , , , , , and . DFT, page 331-339. IEEE Computer Society, (2010)

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Dr. -Ing. Christoph Wenzel University of Stuttgart

Dr. rer. nat. Tim Wendlandt University of Stuttgart

Ingeborg Wenger University of Stuttgart

Florian Wenz University of Stuttgart

Marco Wende University of Stuttgart

 

Other publications of authors with the same name

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Design & Test of Computers, 25 (2): 122-130 (2008)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling., , , , , , , , , and 1 other author(s). Asian Test Symposium, page 90-95. IEEE Computer Society, (2011)Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test., , , , and . ATS, page 173-178. IEEE Computer Society, (2016)A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST., , , , and . ATS, page 203-208. IEEE Computer Society, (2016)Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures., , , , , and . IEICE Transactions, 99-D (11): 2672-2681 (2016)A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing., , , , and . IEICE Transactions, 94-D (4): 833-840 (2011)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , and . IEICE Transactions, 93-D (1): 2-9 (2010)A testable design of logic circuits under highly observable condition., and . ITC, page 955-963. IEEE Computer Society, (1990)