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Disambiguation of "Jiang, Zhigang"

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VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.

, , , , , , and . IEEE Design & Test of Computers, 25 (2): 122-130 (2008)

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Chenming Jiang University of Stuttgart

 

Other publications of authors with the same name

Benefits of a SoC-Specific Test Methodology., , and . IEEE Design & Test of Computers, 20 (3): 68-77 (2003)A method for evaluating environmental performance of machining systems., , , , and . Int. J. Computer Integrated Manufacturing, 25 (6): 488-495 (2012)Research on Dynamic Integrated Energy Efficiency Model of CNC Machine Tools Based on DEVS., , , and . SMC, page 1380-1385. IEEE, (2018)A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing., , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). DFT, page 358-366. IEEE Computer Society, (2010)Composite thermally-induced focusing of a probe beam with Gaussian-distribution propagating through a cesium cell end-pumped by a LD., , , , , , , , , and 1 other author(s). WOCC, page 1-5. IEEE, (2016)Energy Efficiency Evaluation for Iron and Steel High Energy Consumption Enterprise., , , , , , and . ISIA, volume 86 of Communications in Computer and Information Science, page 684-690. Springer, (2010)An integrated model for remanufacturing process route decision., , , and . Int. J. Computer Integrated Manufacturing, 28 (5): 451-459 (2015)A Decision-making Method for Active Remanufacturing Time Based on Environmental and Economic Indicators., , , , and . Int. J. Online Eng., 12 (12): 32-37 (2016)Threshold Testing: Improving Yield for Nanoscale VLSI., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (12): 1883-1895 (2009)