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Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). DFT, page 358-366. IEEE Computer Society, (2010)Physical-design-friendly hierarchical logic built-in self-test - A case study., , , , , , , , , and 1 other author(s). ISQED, page 1-6. IEEE, (2012)Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (2): 299-312 (2010)Practical Challenges in Logic BIST Implementation., , , , , , , and . ATS, page 265. IEEE Computer Society, (2008)Logic BIST Architecture for System-Level Test and Diagnosis., , , , , , , , , and 5 other author(s). Asian Test Symposium, page 21-26. IEEE Computer Society, (2009)A circular pipeline processing based deterministic parallel test pattern generator., , , and . ITC, page 1-8. IEEE Computer Society, (2013)Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard., , , , , , , , , and 6 other author(s). ITC, page 1-9. IEEE Computer Society, (2008)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Design & Test of Computers, 26 (1): 26-35 (2009)