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UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.

, , , , , , and . ITC, page 8. IEEE Computer Society, (2005)

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VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Design & Test of Computers, 25 (2): 122-130 (2008)A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing., , , , and . IEICE Transactions, 94-D (4): 833-840 (2011)Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test., , , , and . ATS, page 173-178. IEEE Computer Society, (2016)A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST., , , , and . ATS, page 203-208. IEEE Computer Society, (2016)High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme., , , , , , , and . IEICE Transactions, 93-D (1): 2-9 (2010)Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures., , , , , and . IEICE Transactions, 99-D (11): 2672-2681 (2016)Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. VLSI Syst., 24 (1): 38-49 (2016)A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits., , , , and . IEICE Transactions, 91-D (3): 667-674 (2008)VLSI testing and test power.. IGCC, page 1-6. IEEE Computer Society, (2011)