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A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits.

, , , , and . IEICE Transactions, 91-D (3): 667-674 (2008)

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Embedded Tutorial on Low Power Test., and . European Test Symposium, page 202-210. IEEE Computer Society, (2007)Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. VLSI Syst., 24 (1): 38-49 (2016)A Testable Design of Logic Circuits under Highly Observable Condition., and . IEEE Trans. Computers, 41 (5): 654-659 (1992)CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing., , , , , , , and . Asian Test Symposium, page 99-104. IEEE Computer Society, (2009)Fault Diagnosis for Physical Defects of Unknown Behaviors., , , and . Asian Test Symposium, page 236-241. IEEE Computer Society, (2003)Session Summary III: Power-Aware Testing: Present and Future., and . Asian Test Symposium, page 220. IEEE Computer Society, (2012)Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (3): 499-512 (2016)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Design & Test of Computers, 25 (2): 122-130 (2008)A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits., , , , and . IEICE Transactions, 91-D (3): 667-674 (2008)