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GPU-Accelerated Simulation of Small Delay Faults

, , , , and . IEEE transactions on computer-aided design of integrated circuits and systems, 36 (5): 829-841 (2017)
DOI: 10.1109/TCAD.2016.2598560

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OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware"., , , , , , and . AHS, page 38-45. IEEE, (2012)Test exploration and validation using transaction level models., , , , , , , and . DATE, page 1250-1253. IEEE, (2009)Scan pattern retargeting and merging with reduced access time., , and . ETS, page 1-7. IEEE Computer Society, (2013)FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects., , , , , and . ITC, page 1-8. IEEE Computer Society, (2014)Modeling, verification and pattern generation for reconfigurable scan networks., , and . ITC, page 1-9. IEEE Computer Society, (2012)An on-chip self-test architecture with test patterns recorded in scan chains., , and . ITC, page 1-10. IEEE, (2016)Power-aware test generation with guaranteed launch safety for at-speed scan testing., , , , , , , and . VTS, page 166-171. IEEE Computer Society, (2011)Efficient fault simulation on many-core processors., , , and . DAC, page 380-385. ACM, (2010)Structure-Oriented Test of Reconfigurable Scan Networks, , and . 2017 IEEE 26th Asian Test Symposium (ATS), page 127-132. Piscataway, IEEE, (2017)Aging monitor reuse for small delay fault testing, , and . 2017 IEEE 35th VLSI Test Symposium (VTS), Piscataway, IEEE, (2017)