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An on-chip self-test architecture with test patterns recorded in scan chains.

, , and . ITC, page 1-10. IEEE, (2016)

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Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Design & Test of Computers, 26 (1): 26-35 (2009)An embedded processor based SOC test platform., , and . ISCAS (3), page 2983-2986. IEEE, (2005)Output-bit selection with X-avoidance using multiple counters for test-response compaction., , , and . ETS, page 1-6. IEEE, (2014)A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip., , and . IEEE Trans. Computers, 67 (9): 1231-1245 (2018)An Efficient BIST Method for Small Buffers., , , and . VTS, page 246-251. IEEE Computer Society, (1999)Improve transition fault diagnosability via observation point insertion., , and . VLSI-DAT, page 1-4. IEEE, (2015)A Complete Logic BIST Technology with No Storage Requirement., and . Asian Test Symposium, page 129-134. IEEE Computer Society, (2010)Transaction Level Modeling and Design Space Exploration for SOC Test Architectures., , , and . Asian Test Symposium, page 200-205. IEEE Computer Society, (2009)An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults., and . ATS, page 306-311. IEEE Computer Society, (2014)An on Chip ADC Test Structure., and . DATE, page 221-225. IEEE Computer Society / ACM, (2000)