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Power-aware test generation with guaranteed launch safety for at-speed scan testing.

, , , , , , , and . VTS, page 166-171. IEEE Computer Society, (2011)

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Fault Diagnosis of Physical Defects Using Unknown Behavior Model., , , and . J. Comput. Sci. Technol., 20 (2): 187-194 (2005)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , and . Asian Test Symposium, page 19-24. IEEE Computer Society, (2013)Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling., , , , , , , , , and 1 other author(s). Asian Test Symposium, page 90-95. IEEE Computer Society, (2011)Towards the next generation of low-power test technologies.. ASICON, page 232-235. IEEE, (2011)VLSI testing and test power.. IGCC, page 1-6. IEEE Computer Society, (2011)Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test., , , , and . ATS, page 173-178. IEEE Computer Society, (2016)A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST., , , , and . ATS, page 203-208. IEEE Computer Society, (2016)Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing., , , , , , and . J. Electronic Testing, 24 (4): 379-391 (2008)Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains., , , , , , , , , and 2 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (3): 455-463 (2011)Test Pattern Modification for Average IR-Drop Reduction., , , , and . IEEE Trans. VLSI Syst., 24 (1): 38-49 (2016)