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Thin-Film FD-SOI BIMOS Topologies for ESD Protection.

L. Conti, S. Cristoloveanu, M. Vinet, and P. Galy. IRPS, page 1-5. IEEE, (2019)

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Delay partitioning helps reducing variability in 3DVLSI.A. Ayres, O. Rozeau, B. Borot, L. Fesquet, and M. Vinet. ESSCIRC, page 75-78. IEEE, (2016)Recent advances in 3D VLSI integration.C. Fenouillet-Beranger, P. Batude, L. Brunet, V. Mazzocchi, C. Lu, F. Deprat, J. Micout, M. Samson, B. Previtali, P. Besombes and 7 other author(s). ICICDT, page 1-4. IEEE, (2016)Piezoresistive transduction optimization of p-doped poly-Silicon NEMS.I. Ouerghi, W. Ludurczak, L. Duraffourg, C. Ladner, A. Oudrhiri, P. Gergaud, M. Vinet, and T. Ernst. ESSDERC, page 149-152. IEEE, (2015)A comprehensive study of monolithic 3D cell on cell design using commercial 2D tool.O. Billoint, H. Sarhan, I. Rayane, M. Vinet, P. Batude, C. Fenouillet-Béranger, O. Rozeau, G. Cibrario, F. Deprat, A. Fustier and 6 other author(s). DATE, page 1192-1196. ACM, (2015)From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges.O. Billoint, H. Sarhan, I. Rayane, M. Vinet, P. Batude, C. Fenouillet-Béranger, O. Rozeau, G. Cibrario, F. Deprat, O. Turkyilmaz and 2 other author(s). ISPD, page 127. ACM, (2015)3D monolithic integration.P. Batude, M. Vinet, A. Pouydebasque, C. Royer, B. Previtali, C. Tabone, J. Hartmann, L. Sanchez, L. Baud, V. Carron and 6 other author(s). ISCAS, page 2233-2236. IEEE, (2011)Opportunities brought by sequential 3D CoolCube™ integration.M. Vinet, P. Batude, C. Fenouillet-Béranger, L. Brunet, V. Mazzocchi, C. Lu, F. Deprat, J. Micout, B. Previtali, P. Besombes and 11 other author(s). ESSDERC, page 226-229. IEEE, (2016)Guidelines for intermediate back end of line (BEOL) for 3D sequential integration.C. Fenouillet-Béranger, S. Beaurepaire, F. Deprat, A. Sousa, L. Brunet, P. Batude, O. Rozeau, F. Andrieu, P. Besombes, M. Samson and 18 other author(s). ESSDERC, page 252-255. IEEE, (2017)Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.F. Andrieu, M. Casse, E. Baylac, P. Perreau, O. Nier, D. Rideau, R. Berthelon, F. Pourchon, A. Pofelski, B. Salvo and 17 other author(s). ESSDERC, page 106-109. IEEE, (2014)Analog performance of strained SOI nanowires down to 10K.B. Paz, M. Pavanello, M. Casse, S. Barraud, G. Reimbold, M. Vinet, and O. Faynot. ESSDERC, page 222-225. IEEE, (2016)

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Thin-Film FD-SOI BIMOS Topologies for ESD Protection.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Thin-Film FD-SOI BIMOS Topologies for ESD Protection.

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Thin-Film FD-SOI BIMOS Topologies for ESD Protection.