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SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.

Y. Yang, J. Park, S. Song, J. Wang, G. Yeap, and S. Jung. IEEE Trans. on Circuits and Systems, 62-I (6): 1538-1545 (2015)

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Sumee Park

Soo Yong Park University of Stuttgart

Other publications of authors with the same name

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.K. Kang, H. Jeong, Y. Yang, J. Park, K. Kim, and S. Jung. IEEE Trans. VLSI Syst., 24 (4): 1342-1350 (2016)High-Order Tensor Regularization With Application to Attribute Ranking.K. Kim, J. Park, and J. Tompkin. CVPR, page 4349-4357. IEEE Computer Society, (2018)Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time.H. Jeong, J. Park, S. Song, and S. Jung. J. Solid-State Circuits, 54 (8): 2304-2315 (2019)Mapping Areas using Computer Vision Algorithms and Drones.B. Alhafni, S. Guedes, L. Ribeiro, J. Park, and J. Lee. CoRR, (2019)Efficient Automatic Original Entry Point Detection.G. Kim, J. Park, Y. Jang, and Y. Park. J. Inf. Sci. Eng., 35 (4): 887-901 (2019)Structural components in functional data.J. Park, T. Gasser, and V. Rousson. Computational Statistics & Data Analysis, 53 (9): 3452-3465 (2009)Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.Y. Yang, J. Park, S. Song, J. Wang, G. Yeap, and S. Jung. IEEE Trans. VLSI Syst., 23 (11): 2748-2752 (2015)SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.Y. Yang, J. Park, S. Song, J. Wang, G. Yeap, and S. Jung. IEEE Trans. on Circuits and Systems, 62-I (6): 1538-1545 (2015)Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM.H. Jeong, J. Park, T. Oh, W. Rim, T. Song, G. Kim, H. Won, and S. Jung. IEEE Trans. on Circuits and Systems, 63-II (11): 1059-1063 (2016)SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis.T. Choi, H. Jeong, Y. Yang, J. Park, and S. Jung. IEEE Trans. on Circuits and Systems, 64-I (8): 2063-2072 (2017)

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Disambiguation of "Park, Juhyun"

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SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.

Please choose a person to relate this publication to

Sumee Park

Soo Yong Park University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Park, Juhyun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.

Please choose a person to relate this publication to

Sumee Park

Soo Yong Park University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.