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Disambiguation of "Yang, Younghwi"

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Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology.

, , , , , and . IEEE Trans. VLSI Syst., 23 (11): 2748-2752 (2015)

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Xiliu Yang University of Stuttgart

Yang Wang University of Stuttgart

Guangpu Yang University of Stuttgart

Hsiu-Yu Yang University of Stuttgart

Peihan Yang University of Stuttgart

 

Other publications of authors with the same name

One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM., , , , and . IEEE Trans. VLSI Syst., 22 (6): 1262-1269 (2014)Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM., , , , , , and . IEEE Trans. on Circuits and Systems, 62-I (4): 1062-1070 (2015)Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory., , , , and . IEEE Trans. VLSI Syst., 23 (4): 752-765 (2015)Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology., , , , , and . IEEE Trans. VLSI Syst., 23 (11): 2748-2752 (2015)SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit., , , , , and . IEEE Trans. on Circuits and Systems, 62-I (6): 1538-1545 (2015)SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis., , , , and . IEEE Trans. on Circuits and Systems, 64-I (8): 2063-2072 (2017)Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits., , , , and . ICECS, page 833-836. IEEE, (2012)Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation., , , , , and . IEEE Trans. VLSI Syst., 24 (4): 1342-1350 (2016)Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology., , , , , and . IEEE Trans. on Circuits and Systems, 63-I (7): 1023-1032 (2016)Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory., , , , , , , and . IEEE Trans. VLSI Syst., 27 (8): 1828-1839 (2019)