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Disambiguation of "Jung, Seong-Ook"

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Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory.

, , , , , , , and . IEEE Trans. VLSI Syst., 27 (8): 1828-1839 (2019)

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Mathias Jung University of Stuttgart

Philipp Junger

Dr. Kerstin Jung University of Stuttgart

Tobias Junginger University of Stuttgart

Univ. -Prof. Dr. -Ing. Hans Christian Jünger University of Stuttgart

 

Other publications of authors with the same name

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator., , , , and . IEEE Trans. VLSI Syst., 24 (4): 1484-1492 (2016)New current-mode sense amplifiers for high density DRAM and PIM architectures., , , , and . ISCAS (4), page 938-941. IEEE, (2001)A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic., , , , , and . ISCAS (2), page 781-784. IEEE, (2004)All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator., , , , and . IEEE Trans. VLSI Syst., 24 (11): 3232-3242 (2016)Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm., , and . IEICE Electronic Express, 13 (12): 20160287 (2016)Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time., , , and . J. Solid-State Circuits, 54 (8): 2304-2315 (2019)A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories., , , , , and . IEEE Trans. VLSI Syst., 27 (2): 387-397 (2019)SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation., and . ISCAS, page 1-4. IEEE, (2018)Minimum delay optimization for domino circuits - a coupling-aware approach., , , and . ACM Trans. Design Autom. Electr. Syst., 8 (2): 202-213 (2003)A comparative study of STT-MTJ based non-volatile flip-flops., , , , and . ISCAS, page 109-112. IEEE, (2013)