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Disambiguation of "Jeong, Hanwool"

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Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time.

, , , and . J. Solid-State Circuits, 54 (8): 2304-2315 (2019)

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Moon Kwang Jeong University of Stuttgart

Moon Young Jeong University of Stuttgart

 

Other publications of authors with the same name

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM., , , , and . IEEE Trans. VLSI Syst., 23 (7): 1370-1374 (2015)Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter., , , , and . ICECS, page 400-403. IEEE, (2015)Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_MIN$ Improvement and Energy Saving., , , , , , , and . J. Solid-State Circuits, 54 (3): 896-906 (2019)Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM., , , , , , and . IEEE Trans. on Circuits and Systems, 62-I (6): 1555-1563 (2015)One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM., , , , and . IEEE Trans. VLSI Syst., 22 (6): 1262-1269 (2014)Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM., , , , , , and . IEEE Trans. on Circuits and Systems, 62-I (4): 1062-1070 (2015)Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time., , , and . J. Solid-State Circuits, 54 (8): 2304-2315 (2019)Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits., , , , and . ICECS, page 833-836. IEEE, (2012)Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology., , , , , and . IEEE Trans. on Circuits and Systems, 63-I (7): 1023-1032 (2016)Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation., , , , , and . IEEE Trans. VLSI Syst., 24 (4): 1342-1350 (2016)