%0 Journal Article %1 journals/tcas/ChoiJYPJ17 %A Choi, Tae Hoon %A Jeong, Hanwool %A Yang, Younghwi %A Park, Juhyun %A Jung, Seong-Ook %D 2017 %J IEEE Trans. on Circuits and Systems %K dblp %N 8 %P 2063-2072 %T SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI64.html#ChoiJYPJ17 %V 64-I

@article{journals/tcas/ChoiJYPJ17, added-at = {2019-01-19T00:00:00.000+0100}, author = {Choi, Tae Hoon and Jeong, Hanwool and Yang, Younghwi and Park, Juhyun and Jung, Seong-Ook}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/23ec6e0e213c4b45356dd9fecbf715ee5/dblp}, ee = {https://doi.org/10.1109/TCSI.2017.2685634}, interhash = {f885fe75a941dcc257efd6bbe18cef95}, intrahash = {3ec6e0e213c4b45356dd9fecbf715ee5}, journal = {IEEE Trans. on Circuits and Systems}, keywords = {dblp}, number = 8, pages = {2063-2072}, timestamp = {2019-09-27T11:52:50.000+0200}, title = {SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI64.html#ChoiJYPJ17}, volume = {64-I}, year = 2017 }