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Disambiguation of "Jung, Seong-Ook"

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SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit.

, , , , , and . IEEE Trans. on Circuits and Systems, 62-I (6): 1538-1545 (2015)

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Mathias Jung University of Stuttgart

Philipp Junger

Dr. Kerstin Jung University of Stuttgart

Tobias Junginger University of Stuttgart

Univ. -Prof. Dr. -Ing. Hans Christian Jünger University of Stuttgart

 

Other publications of authors with the same name

An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management., , , , and . IEEE Trans. VLSI Syst., 23 (8): 1508-1517 (2015)An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM., , , , and . IEEE Trans. VLSI Syst., 22 (7): 1620-1624 (2014)All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM., , , , and . IEEE Trans. on Circuits and Systems, 62-II (11): 1023-1027 (2015)Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector., , and . IEEE Trans. on Circuits and Systems, 61-II (1): 1-5 (2014)Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM., , , , and . IEEE Trans. on Circuits and Systems, 62-I (8): 2091-2102 (2015)A comparative study of STT-MTJ based non-volatile flip-flops., , , , and . ISCAS, page 109-112. IEEE, (2013)Process variation tolerant all-digital multiphase DLL for DDR3 interface., , , , , , and . CICC, page 1-4. IEEE, (2010)High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator., , , , and . IEEE Trans. VLSI Syst., 24 (4): 1484-1492 (2016)A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic., , , , , and . ISCAS (2), page 781-784. IEEE, (2004)New current-mode sense amplifiers for high density DRAM and PIM architectures., , , , and . ISCAS (4), page 938-941. IEEE, (2001)