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Disambiguation of "Jung, Dong-Hoon"

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An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management.

, , , , and . IEEE Trans. VLSI Syst., 23 (8): 1508-1517 (2015)

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Mathias Jung University of Stuttgart

Laura-Ann Dönges University of Stuttgart

Philipp Junger

Dr. Kerstin Jung University of Stuttgart

Jong Hyun Jung University of Stuttgart

 

Other publications of authors with the same name

ADDLL for Clock-Deskew Buffer in High-Performance SoCs., , , and . IEEE Trans. VLSI Syst., 21 (7): 1368-1373 (2013)Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs., , , , and . IEEE Trans. VLSI Syst., 23 (3): 413-421 (2015)Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface., , , , , , , and . IEEE Trans. on Circuits and Systems, 59-I (10): 2186-2196 (2012)All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme., , , and . IEEE Trans. VLSI Syst., 24 (3): 1015-1024 (2016)Lessons Learned from an Auditory-vibrotactile Sensory Experience in the Museum., , , , and . ISS, page 373-378. ACM, (2019)A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface., , and . IEEE Trans. Consumer Electronics, 56 (4): 2400-2405 (2010)A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction., , , and . ESSCIRC, page 181-184. IEEE, (2012)All-digital 90° phase-shift DLL with a dithering jitter suppression scheme., , , , and . CICC, page 1-4. IEEE, (2013)A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator., , and . IEEE Trans. on Circuits and Systems, 59-I (9): 1860-1870 (2012)An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management., , , , and . IEEE Trans. VLSI Syst., 23 (8): 1508-1517 (2015)