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Disambiguation of "Rim, Woojin"

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Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM.

, , , , , , , and . IEEE Trans. on Circuits and Systems, 63-II (11): 1059-1063 (2016)

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Other publications of authors with the same name

Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM., , , , , , , and . IEEE Trans. on Circuits and Systems, 63-II (11): 1059-1063 (2016)A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 52 (1): 240-249 (2017)12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis., , , , , , , , , and 13 other author(s). ISSCC, page 208-209. IEEE, (2017)17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization., , , , , , , , , and 8 other author(s). ISSCC, page 306-307. IEEE, (2016)Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics., , and . IEEE Trans. on Circuits and Systems, 59-II (9): 587-591 (2012)A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit., , , , , , , and . IEEE J. Solid State Circuits, 57 (1): 236-244 (2022)A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications., , , , , , , , , and 4 other author(s). ISSCC, page 198-200. IEEE, (2018)Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_MIN$ Improvement and Energy Saving., , , , , , , and . J. Solid-State Circuits, 54 (3): 896-906 (2019)A 14 nm FinFET 128 Mb SRAM With V $_MIN$ Enhancement Techniques for Low-Power Applications., , , , , , , , , and 10 other author(s). J. Solid-State Circuits, 50 (1): 158-169 (2015)