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Disambiguation of "Sparsø, Jens"

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Models of Communication for Multicore Processors.

, , and . ISORC Workshops, page 9-16. IEEE Computer Society, (2015)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Univ. -Prof. Dr. Jens Brockmeyer University of Stuttgart

Jens Wizl University of Stuttgart

Jens Keim University of Stuttgart

GALÆXI Validation: Taylor-Green Vortex, , , , , , , , and . Dataset, (2024)Related to: Kempf, Daniel et al. “GALÆXI: Solving complex compressible flows with high-order discontinuous Galerkin methods on accelerator-based systems.” (2024). arXiv: 2404.12703.
GALÆXI Validation: Taylor-Green Vortex, , , , , , , , and . Dataset, (2024)Related to: Kempf, Daniel et al. “GALÆXI: Solving complex compressible flows with high-order discontinuous Galerkin methods on accelerator-based systems.” (2024). arXiv: 2404.12703.GALÆXI Verification: Convergence Tests, , , , , , , , and . Dataset, (2024)Related to: Kempf, Daniel et al. “GALÆXI: Solving complex compressible flows with high-order discontinuous Galerkin methods on accelerator-based systems.” (2024). arXiv: 2404.12703.GALÆXI Scaling, , , , , , , , and . Dataset, (2024)Related to: Kempf, Daniel et al. “GALÆXI: Solving complex compressible flows with high-order discontinuous Galerkin methods on accelerator-based systems.” (2024). arXiv: 2404.12703.

Jens Müller University of Stuttgart

Jens Anders

 

Other publications of authors with the same name

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology., and . NOCS, page 55-64. IEEE Computer Society, (2008)Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend., , and . IEEE Trans. VLSI Syst., 17 (2): 248-261 (2009)Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation., , , , , and . IEEE Trans. VLSI Syst., 24 (2): 479-492 (2016)A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip., , , and . Journal of Systems Architecture - Embedded Systems Design, (2017)Demonstration of a Time-predictable Flight Controller on a Multicore Processor., , , , , , and . ISORC, page 95-96. IEEE, (2019)Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip., , , and . DSD, page 319-326. IEEE Computer Society, (2013)Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip., , and . CODES+ISSS, page 481-490. ACM, (2009)A Time-Predictable Memory Network-on-Chip., , , and . WCET, volume 39 of OASIcs, page 53-62. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2014)A Time-predictable TTEthenet Node., , , and . ISORC, page 229-233. IEEE, (2019)A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 301-310. Springer, (2004)