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A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip., , , and . Journal of Systems Architecture - Embedded Systems Design, (2017)A Multicore Processor for Time-Critical Applications., , and . IEEE Design & Test, 35 (2): 38-47 (2018)High-level synthesis for reduction of WCET in real-time systems., , and . NORCAS, page 1-6. IEEE, (2017)A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems., , and . ISORC, page 92-100. IEEE Computer Society, (2017)A Time-predictable TTEthenet Node., , , and . ISORC, page 229-233. IEEE, (2019)Reconfiguration in FPGA-based multi-core platforms for hard real-time applications., , and . ReCoSoC, page 1-8. IEEE, (2016)S4NOC: a minimalistic network-on-chip for real-time multicores., , and . NoCArc@MICRO, page 8:1-8:6. ACM, (2019)Using dynamic partial reconfiguration of FPGAs in real-Time systems., , , and . Microprocessors and Microsystems - Embedded Hardware Design, (2018)A Minimal Network Interface for a Simple Network-on-Chip., , and . ARCS, volume 11479 of Lecture Notes in Computer Science, page 295-307. Springer, (2019)Interfacing hardware accelerators to a time-division multiplexing network-on-chip., , , and . NORCAS, page 1-4. IEEE, (2015)