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A Time-Predictable Memory Network-on-Chip.

M. Schoeberl, D. Chong, W. Puffitsch, and J. Sparsø. WCET, volume 39 of OASIcs, page 53-62. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2014)

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Univ. -Prof. Dr. Jens Brockmeyer University of Stuttgart

Jens Wizl University of Stuttgart

Jens Müller University of Stuttgart

Jens Anders

Jens Hamann University of Stuttgart

Other publications of authors with the same name

ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology.M. Stensgaard, and J. Sparsø. NOCS, page 55-64. IEEE Computer Society, (2008)Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend.S. Nielsen, J. Sparsø, and J. Madsen. IEEE Trans. VLSI Syst., 17 (2): 248-261 (2009)Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation.E. Kasapaki, M. Schoeberl, R. Sorensen, C. Muller, K. Goossens, and J. Sparsø. IEEE Trans. VLSI Syst., 24 (2): 479-492 (2016)Demonstration of a Time-predictable Flight Controller on a Multicore Processor.O. Baris, S. Majumder, T. Strøm, A. la Cour-Harbo, J. Sparsø, T. Bak, and M. Schoeberl. ISORC, page 95-96. IEEE, (2019)A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip.R. Sørensen, L. Pezzarossa, M. Schoeberl, and J. Sparsø. Journal of Systems Architecture - Embedded Systems Design, (2017)Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip.M. Stuart, M. Stensgaard, and J. Sparsø. CODES+ISSS, page 481-490. ACM, (2009)Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip.E. Kasapaki, J. Sparsø, R. Sorensen, and K. Goossens. DSD, page 319-326. IEEE Computer Society, (2013)A Time-Predictable Memory Network-on-Chip.M. Schoeberl, D. Chong, W. Puffitsch, and J. Sparsø. WCET, volume 39 of OASIcs, page 53-62. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2014)A Time-predictable TTEthenet Node.M. Lund, L. Pezzarossa, J. Sparsø, and M. Schoeberl. ISORC, page 229-233. IEEE, (2019)A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.T. Bjerregaard, S. Mahadevan, and J. Sparsø. PATMOS, volume 3254 of Lecture Notes in Computer Science, page 301-310. Springer, (2004)