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Disambiguation of "Aseron, Paolo A."

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A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 46-48. IEEE, (2018)

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A. Laukemann

PD Dr. Paolo Malgaretti University of Stuttgart

A. Laukemann

A. Laukemann

A. Vo{\ss}

 

Other publications of authors with the same name

4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging., , , , , , and . ISSCC, page 1-3. IEEE, (2015)Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops., , , , , , , , , and 1 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 208-217 (2011)A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS., , , , , , , , , and 27 other author(s). ISSCC, page 46-48. IEEE, (2018)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS., , , , , , , , , and 2 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control., , , , , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2017-2025 (2011)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 46 (1): 194-208 (2011)2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 44 (1): 174-185 (2009)