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Disambiguation of "Karnik, Tanay"

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Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.

, , , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 208-217 (2011)

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Other publications of authors with the same name

Accurate Estimation of SRAM Dynamic Stability., , , , , and . IEEE Trans. VLSI Syst., 16 (12): 1639-1647 (2008)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters., , , , , , and . J. Solid-State Circuits, 42 (1): 66-73 (2007)An empirical model for accurate estimation of routing delay in FPGAs., and . ICCAD, page 328-331. IEEE Computer Society / ACM, (1995)Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors., , , , , , , and . DAC, page 486-491. ACM, (2002)Circuit techniques for dynamic variation tolerance., , , , , , and . DAC, page 4-7. ACM, (2009)Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies., , and . VLSI Design, page 5-7. IEEE Computer Society, (2006)Design for test and reliability in ultimate CMOS., , , , , , , , , and 4 other author(s). DATE, page 677-682. IEEE, (2012)Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency., , , , , , , , , and . CICC, page 1-4. IEEE, (2010)Design of sub-90nm Circuits and Design Methodologies., , , , and . ISQED, page 3-4. IEEE Computer Society, (2005)