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Design for test and reliability in ultimate CMOS., , , , , , , , , and 4 other author(s). DATE, page 677-682. IEEE, (2012)Distributed hardware matcher framework for SoC survivability., and . DATE, page 305-310. IEEE, (2011)Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency., , , , , , , , , and . CICC, page 1-4. IEEE, (2010)Trading off Cache Capacity for Reliability to Enable Low Voltage Operation., , , , , and . ISCA, page 203-214. IEEE Computer Society, (2008)Trading Off Cache Capacity for Low-Voltage Operation., , , , , and . IEEE Micro, 29 (1): 96-103 (2009)Adaptive Cache Design to Enable Reliable Low-Voltage Operation., , , , and . IEEE Trans. Computers, 60 (1): 50-63 (2011)Advances of the Counterflow Pipeline Microarchitecture., , and . HPCA, page 230-236. IEEE Computer Society, (1997)Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance., , , , and . MEMSYS, page 179-190. ACM, (2015)Reducing cache and TLB power by exploiting memory region and privilege level semantics., , , , , , and . Journal of Systems Architecture - Embedded Systems Design, 59 (6): 279-295 (2013)Design, implementation, and verification of active cache emulator (ACE)., , and . FPGA, page 63-72. ACM, (2006)