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Disambiguation of "Howard, Jason"

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2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.

, , , , , , , , , , and . ISSCC, page 274-275. IEEE, (2008)

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Astrid Howard University of Stuttgart

Jason Kennedy Appelbaum University of Stuttgart

 

Other publications of authors with the same name

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 46 (1): 184-193 (2011)A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS., , , , , , , , , and 20 other author(s). ISSCC, page 108-109. IEEE, (2010)An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process., , , , , , , , , and 1 other author(s). ISSCC, page 274-275. IEEE, (2008)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)The 48-core SCC Processor: the Programmer's View., , , , , , , , , and 1 other author(s). SC, page 1-11. IEEE, (2010)A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 42 (1): 233-242 (2007)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)Resiliency for many-core system on a chip., , , , , , and . ASP-DAC, page 388-389. IEEE, (2014)2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 44 (1): 174-185 (2009)