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Test implications and challenges in near threshold computing special session., , , and . VTS, page 1. IEEE Computer Society, (2016)IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS., , , , and . IEEE Micro, 33 (2): 28-36 (2013)Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies., and . IEEE Design & Test of Computers, 27 (4): 6-9 (2010)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . J. Solid-State Circuits, 46 (4): 757-766 (2011)An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 843-856 (2021)A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm., , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS., , , , , , , , , and 20 other author(s). ISSCC, page 108-109. IEEE, (2010)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 46 (1): 184-193 (2011)Introduction to the Special Section on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)., and . J. Solid-State Circuits, 54 (11): 2919-2920 (2019)