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Disambiguation of "Hoskote, Yatin"

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A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.

, , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)

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A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . J. Solid-State Circuits, 46 (4): 757-766 (2011)An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)Learning-Based Power Modeling of System-Level Black-Box IPs., , , , , and . ICCAD, page 847-853. IEEE, (2015)Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator design., , and . ASP-DAC, page 219-224. IEEE, (2014)A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS., , , , , , , , , and 27 other author(s). ISSCC, page 46-48. IEEE, (2018)A 5-GHz Mesh Interconnect for a Teraflops Processor., , , , and . IEEE Micro, 27 (5): 51-61 (2007)A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip., , , , , , , , and . VLSI Design, page 292-297. IEEE Computer Society, (2012)High level design for wearables and IoT., and . ICCAD, page 72. IEEE, (2014)Automatic generation of custom SIMD instructions for Superword Level Parallelism., and . DATE, page 1-6. European Design and Automation Association, (2014)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 43 (1): 29-41 (2008)