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A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.

, , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)

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Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 46 (1): 184-193 (2011)A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS., , , , , , , , , and 20 other author(s). ISSCC, page 108-109. IEEE, (2010)A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm., , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS., , , and . VLSI Design, page 301-306. IEEE Computer Society, (2009)A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip., , , , , , , , and . VLSI Design, page 292-297. IEEE Computer Society, (2012)A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores., , , , and . VLSI Design, page 273-278. IEEE Computer Society, (2008)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling., , , , , , , , , and 6 other author(s). J. Solid-State Circuits, 46 (1): 173-183 (2011)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). J. Solid-State Circuits, 43 (1): 29-41 (2008)