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Disambiguation of "Borkar, Nitin"

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A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm.

, , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)

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An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . J. Solid-State Circuits, 46 (4): 757-766 (2011)System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. VLSI Syst., 24 (12): 3468-3476 (2016)Design Challenges in Sub-100nm High Performance Microprocessors., , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)A 5-GHz Mesh Interconnect for a Teraflops Processor., , , , and . IEEE Micro, 27 (5): 51-61 (2007)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip., , , , , , , , and . VLSI Design, page 292-297. IEEE Computer Society, (2012)The 48-core SCC Processor: the Programmer's View., , , , , , , , , and 1 other author(s). SC, page 1-11. IEEE, (2010)A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 42 (1): 233-242 (2007)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 46 (1): 184-193 (2011)