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Disambiguation of "Tschanz, James W."

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Design Challenges in Sub-100nm High Performance Microprocessors.

, , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)

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Univ. -Prof. Dr. James Foster University of Stuttgart

Samuel James Tovey University of Stuttgart

Tim W{\"{u}}rtele

Tim W{\"{u}}rtele

Kent W. Stewart

 

Other publications of authors with the same name

A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response., , , , , , , and . VLSI Circuits, page 124-. IEEE, (2019)Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance., , , , , , , and . J. Solid-State Circuits, 44 (1): 49-63 (2009)Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays., , , , , , , and . J. Solid-State Circuits, 46 (4): 797-805 (2011)Resilient microprocessor design for improving performance and energy efficiency., and . ICCAD, page 85-88. IEEE, (2010)Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques., , , , and . IEEE Trans. on Circuits and Systems, 53-I (9): 1928-1933 (2006)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS., , , , , , , and . J. Solid-State Circuits, 53 (4): 1038-1048 (2018)Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS., , , , , and . J. Solid-State Circuits, 50 (8): 1809-1819 (2015)Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 51 (1): 18-30 (2016)A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit., , and . DFT, page 343-351. IEEE Computer Society, (2008)