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A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response.

, , , , , , , and . VLSI Circuits, page 124-. IEEE, (2019)

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4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging., , , , , , and . ISSCC, page 1-3. IEEE, (2015)8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating., , , , , , , , and . ISSCC, page 152-153. IEEE, (2016)A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems., , , and . ASP-DAC, page 847-852. IEEE, (2009)TapeCache: a high density, energy efficient cache based on domain wall memory., , , , , and . ISLPED, page 185-190. ACM, (2012)Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting., , , , , and . BioCAS, page 1-4. IEEE, (2018)A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response., , , , , , , and . VLSI Circuits, page 124-. IEEE, (2019)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems., , and . DFT, page 323-331. IEEE Computer Society, (2008)Ultra low energy analog image processing using spin based neurons., , , and . NANOARCH, page 211-217. ACM, (2012)A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging., , , , , , and . J. Solid-State Circuits, 51 (1): 117-129 (2016)