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4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.

J. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen, C. Augustine, J. Tschanz, and V. De. ISSCC, page 1-3. IEEE, (2015)

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Other publications of authors with the same name

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.S. Kim, Y. Shih, K. Mazumdar, R. Jain, J. Ryan, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A novel slope detection technique for robust STTRAM sensing.S. Motaman, S. Ghosh, and J. Kulkarni. ISLPED, page 7-12. IEEE, (2015)Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design.V. Saripalli, S. Datta, V. Narayanan, and J. Kulkarni. NANOARCH, page 45-52. IEEE Computer Society, (2011)Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor.M. Meterelliyoz, P. Song, F. Stellari, J. Kulkarni, and K. Roy. IEEE Trans. on Circuits and Systems, 57-I (8): 1838-1847 (2010)A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.J. Kulkarni, K. Kim, and K. Roy. ISLPED, page 171-176. ACM, (2007)4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging.J. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen, C. Augustine, J. Tschanz, and V. De. ISSCC, page 1-3. IEEE, (2015)8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating.M. Cho, S. Kim, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, and V. De. ISSCC, page 152-153. IEEE, (2016)Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design.J. Kulkarni, and K. Roy. IEEE Trans. VLSI Syst., 20 (2): 319-332 (2012)A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array.J. Kulkarni, A. Goel, P. Ndai, and K. Roy. IEEE Trans. VLSI Syst., 19 (9): 1727-1730 (2011)Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations.M. Meterelliyoz, J. Kulkarni, and K. Roy. IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (1): 2-13 (2010)

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Disambiguation of "Kulkarni, Jaydeep P."