%0 Conference Paper %1 conf/isscc/ChoKTAKRTKD16 %A Cho, Minki %A Kim, Stephen T. %A Tokunaga, Carlos %A Augustine, Charles %A Kulkarni, Jaydeep P. %A Ravichandran, Krishnan %A Tschanz, James %A Khellah, Muhammad M. %A De, Vivek %B ISSCC %D 2016 %I IEEE %K dblp %P 152-153 %T 8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2016.html#ChoKTAKRTKD16 %@ 978-1-4673-9467-3

@inproceedings{conf/isscc/ChoKTAKRTKD16, added-at = {2016-03-02T00:00:00.000+0100}, author = {Cho, Minki and Kim, Stephen T. and Tokunaga, Carlos and Augustine, Charles and Kulkarni, Jaydeep P. and Ravichandran, Krishnan and Tschanz, James and Khellah, Muhammad M. and De, Vivek}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2619adf67d2209c0d884c74d185dfb532/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2016}, ee = {http://dx.doi.org/10.1109/ISSCC.2016.7417952}, interhash = {d104c1d32da2df6ed55bf434506fe76e}, intrahash = {619adf67d2209c0d884c74d185dfb532}, isbn = {978-1-4673-9467-3}, keywords = {dblp}, pages = {152-153}, publisher = {IEEE}, timestamp = {2016-03-03T10:32:31.000+0100}, title = {8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2016.html#ChoKTAKRTKD16}, year = 2016 }