PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Borkar, Nitin"

Author of the publication

copydeleteadd this publication to your clipboard
Design Challenges in Sub-100nm High Performance Microprocessors.

, , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Borkar, Nitin
add a person with the name Borkar, Nitin
 

Other publications of authors with the same name

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. VLSI Syst., 24 (12): 3468-3476 (2016)An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . J. Solid-State Circuits, 46 (4): 757-766 (2011)Design Challenges in Sub-100nm High Performance Microprocessors., , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 42 (1): 233-242 (2007)A 5-GHz Mesh Interconnect for a Teraflops Processor., , , , and . IEEE Micro, 27 (5): 51-61 (2007)The 48-core SCC Processor: the Programmer's View., , , , , , , , , and 1 other author(s). SC, page 1-11. IEEE, (2010)A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip., , , , , , , , and . VLSI Design, page 292-297. IEEE Computer Society, (2012)Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor., , , , , , , , , and 2 other author(s). ISSCC, page 174-175. IEEE, (2010)A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm., , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)