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A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

M. Khellah, D. Somasekhar, Y. Ye, N. Kim, J. Howard, G. Ruhl, M. Sunna, J. Tschanz, N. Borkar, F. Hamzaoglu, G. Pandya, A. Farhang, K. Zhang, and V. De. J. Solid-State Circuits, 42 (1): 233-242 (2007)

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Ye Feng University of Stuttgart

Weizhou Ye University of Stuttgart

Other publications of authors with the same name

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses.M. Ghoneima, M. Khellah, J. Tschanz, Y. Ye, N. Kurd, J. Barkatullah, S. Nimmagadda, Y. Ismail, and V. De. IEEE Trans. on Circuits and Systems, 55-I (7): 1904-1910 (2008)Online sequential extreme learning machine in nonstationary environments.Y. Ye, S. Squartini, and F. Piazza. Neurocomputing, (2013)ELM-based Algorithms for Nonstationary Volterra System Identification.Y. Ye, S. Squartini, and F. Piazza. WIRN, volume 234 of Frontiers in Artificial Intelligence and Applications, page 77-84. IOS Press, (2011)Design and optimization of dual-threshold circuits for low-voltage low-power applications.L. Wei, Z. Chen, K. Roy, M. Johnson, Y. Ye, and V. De. IEEE Trans. VLSI Syst., 7 (1): 16-24 (1999)A Graph-Based Synthesis Algorithm for AND/XOR Networks.Y. Ye, and K. Roy. DAC, page 107-112. ACM Press, (1997)Dynamic noise analysis in precharge-evaluate circuits.D. Somasekhar, S. Choi, K. Roy, Y. Ye, and V. De. DAC, page 243. ACM, (2000)Quasi-static energy recovery logic and supply-clock generation circuits.Y. Ye, K. Roy, and G. Stamoulis. ISLPED, page 96-99. ACM, (1997)Incremental-Based Extreme Learning Machine Algorithms for Time-Variant Neural Networks.Y. Ye, S. Squartini, and F. Piazza. ICIC (1), volume 6215 of Lecture Notes in Computer Science, page 9-16. Springer, (2010)Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications.L. Wei, Z. Chen, K. Roy, Y. Ye, and V. De. DAC, page 430-435. ACM Press, (1999)Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, and V. De. IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)

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Disambiguation of "Ye, Yibin"

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A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

Please choose a person to relate this publication to

Ye Feng University of Stuttgart

Weizhou Ye University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Ye, Yibin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.

Please choose a person to relate this publication to

Ye Feng University of Stuttgart

Weizhou Ye University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
DOI
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A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor.