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Disambiguation of "Keshavarzi, Ali"

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Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.

, , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)

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Ali Salehi University of Stuttgart

Layal Ali University of Stuttgart

Dr. -Ing. Ali Jamshed University of Stuttgart

Ali Hangi University of Stuttgart

Ali Nakhaee University of Stuttgart

 

Other publications of authors with the same name

Test Methodologies in the Deep Submicron Era - Analog, Mixed-Signal, and RF., , , and . VLSI Design, page 12-13. IEEE Computer Society, (2005)Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs., , , , , , , and . ISLPED, page 207-212. ACM, (2001)Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power., , , and . ISCAS (1), page 9-12. IEEE, (2005)Parameter variations and impact on circuits and microarchitecture., , , , , and . DAC, page 338-342. ACM, (2003)2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 44 (1): 174-185 (2009)Thermal Management of High Performance Microprocessors., , , and . DFT, page 313-319. IEEE Computer Society, (2003)Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism., , , , and . ITC, page 1276-1284. IEEE Computer Society, (2004)A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs., , , , and . DATE, page 206-211. IEEE Computer Society, (2005)Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits., , , , , , , and . IEEE Des. Test Comput., 19 (5): 36-43 (2002)IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions., , , and . IEEE Design & Test of Computers, 19 (2): 24-33 (2002)