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Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.

F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, and V. De. IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)

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Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.D. Somasekhar, B. Srinivasan, G. Pandya, F. Hamzaoglu, M. Khellah, T. Karnik, and K. Zhang. J. Solid-State Circuits, 45 (4): 751-758 (2010)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.Y. Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y. Ng, L. Wei, Y. Zhang, K. Zhang, and M. Bohr. ISSCC, page 456-457. IEEE, (2009)Circuit-level techniques to control gate leakage for sub-100nm CMOS.F. Hamzaoglu, and M. Stan. ISLPED, page 60-63. ACM, (2002)A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology.F. Hamzaoglu, U. Arslan, N. Bisnik, S. Ghosh, M. Lal, N. Lindert, M. Meterelliyoz, R. Osborne, J. Park, S. Tomishima and 2 other author(s). J. Solid-State Circuits, 50 (1): 150-157 (2015)A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.H. Nho, P. Kolar, F. Hamzaoglu, Y. Wang, E. Karl, Y. Ng, U. Bhattacharya, and K. Zhang. ISSCC, page 346-347. IEEE, (2010)2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology.M. Meterelliyoz, F. Al-amoody, U. Arslan, F. Hamzaoglu, L. Hood, M. Lal, J. Miller, A. Ramasundar, D. Soltman, I. Wan and 2 other author(s). VLSIC, page 1-2. IEEE, (2014)A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology.F. Hamzaoglu, K. Zhang, Y. Wang, H. Ahn, U. Bhattacharya, Z. Chen, Y. Ng, A. Pavlov, K. Smits, and M. Bohr. ISSCC, page 376-377. IEEE, (2008)Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, and V. De. IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)Session 7 overview: Non-volatile memory solutions: Memory subcommittee.F. Hamzaoglu, and T. Kono. ISSCC, page 126-127. IEEE, (2015)F2: Memory trends: From big data to wearable devices.J. Chang, L. Chang, A. Dupret, C. Kim, F. Hamzaoglu, and T. Yoshikawa. ISSCC, page 1-2. IEEE, (2015)

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Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.

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Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache.