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Disambiguation of "Ng, Yong-Gee"

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A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.

, , , , , , , and . ISSCC, page 346-347. IEEE, (2010)

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apl. Prof. Dr. Yong Cui University of Stuttgart

Yong Lu University of Stuttgart

Dr. Quynh Ngo University of Stuttgart

San Lam Ng University of Stuttgart

Thi Hue Nguyen University of Stuttgart

 

Other publications of authors with the same name

A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation., , , , , , , and . ISSCC, page 346-347. IEEE, (2010)A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 51 (1): 222-229 (2016)A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology., , , , , , , , , and . ISSCC, page 376-377. IEEE, (2008)A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management., , , , , , , , and . J. Solid-State Circuits, 45 (1): 103-110 (2010)A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (1): 150-158 (2013)A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry., , , , , , , , and . ISSCC, page 230-232. IEEE, (2012)A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation., , , , , , , and . J. Solid-State Circuits, 46 (1): 76-84 (2011)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications., , , , , , , , , and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management., , , , , , , , and . ISSCC, page 456-457. IEEE, (2009)